Integrated circuits having memory arrays that are designed and manufactured with memory built-in self test (MBIST) circuitry are well-known in the art. An example of an integrated circuit incorporating MBIST circuitry is set forth in U.S. Pat. No. 7,340,658 that is assigned to the assignee of the present invention. That patent also provides background information regarding the utility and advantages provided by MBST circuitry in the design and manufacturer of integrated circuits.
Integrated circuit employing MBIST generally include multiple different size arrays of memory elements that require testing. Typically, during MBST testing, a test vector is written into an array and then a read operation is performed with the results analyzed to confirm proper operation of the array under the test vector. Within a given component or section of an integrated circuit, each array of that component is conventionally tested in series in order to analyze any result of the application of the respective test vector with the respective array.